A) Field of the Invention
The present invention relates to a semiconductor device having a resistor element and its manufacture method, and more particularly to a semiconductor device using as a resistor element an impurity diffusion region formed in a surface layer of a semiconductor substrate.
B) Description of the Related Art
Resistor elements are used in a semiconductor integrated circuit. For example, in an input/output circuit, a protective circuit is constituted of a MOS type field effect transistor and a resistor in order to protect internal circuits from electrostatic breakdown. A semiconductor integrated circuit generally uses a conductive film resistor element made of polysilicon or the like formed at the same time when the gate electrode of a field effect transistor is formed or a diffusion layer resistor element formed at the same time when the source and drain regions of a field effect transistor are formed. The resistances of the gate electrode, source and drain diffusion layers are preferably set low from the viewpoint of the performance of a field effect transistor. From this reason, the conductive film formed at the same time when the gate electrode is formed and the diffusion layer formed at the same time when the source and drain regions are formed are not suitable for forming a high resistance element.
Japanese Patent Laid-open Publication No. HEI-11-238807 discloses a method of realizing a high resistance element by utilizing the well just under an element isolation insulating film of a shallow trench isolation (STI) structure.
FIG. 5 is a cross sectional view of a resistor element disclosed in Japanese Patent Laid-open Publication No. HEI-11-238807. An n-type well 101 is formed in a surface layer of a p-type silicon substrate 100. A p-type well 102 is formed in the n-type well 101. The p-type well 102 is formed at the same time when a p-type well is formed in which an NMOS transistor is to be disposed. An element isolation insulation film 103 is formed on the substrate surface, and active regions are defined in different areas of the surface layer of the p-type well 102. In the surface layers of the two active regions, p-type diffusion regions 104 and 105 are formed. The p-type well 102 constitutes a resistor element having the p-type diffusion regions as current input/output ports.
A method of forming the resistor element shown in FIG. 5 will be briefly described. A mask pattern of silicon nitride or the like is formed on the silicon substrate 100. By using the mask pattern as an etching mask, the silicon substrate 100 is etched to form a shallow trench. A silicon oxide film is deposited on the silicon substrate 100, the silicon oxide film being filled in the shallow trench.
This silicon oxide film is subjected to chemical mechanical polishing (CMP) to expose the mask pattern. Silicon oxide left in the shallow trench constitutes the element isolation insulating film 103. The exposed mask pattern is removed and thereafter ion implantation processes are executed to form the n-type well 101, p-type well 102 and p-type diffusion layers 104 and 105.
As the area where the element isolation insulating film 103 becomes broad, the flatness of the surface after CMP is degraded because of a polishing speed difference between silicon oxide and silicon nitride. In order to prevent the flatness from being degraded, a dummy active regions are disposed in the region of the element isolation insulating film 103. These dummy regions are automatically designed by CAD when patterns are designed.
FIG. 6 is a cross sectional view of a resistor element with dummy active regions 106. A plurality of dummy regions 106 are disposed in a p-type well 102.
In the ion implantation process of forming wells, impurity ions are implanted through the element isolation insulating film 103 into the regions just under the element isolation insulating film 103. The depth of the well is deeper in the active regions 106 than in the regions just under the element isolation insulating film 103, because of the influence of channeling.
FIG. 7 is a graph showing an example of an impurity concentration distribution along a depth direction. The abscissa represents a position along the depth direction in the unit of “μm” and the ordinate represents an impurity concentration in the unit of “cm−3”. A solid line a indicates the impurity concentration distribution in the region where the element isolation insulating film is formed, and a solid line b indicates the impurity concentration distribution in the active region. The position at a depth of about 0.04 μm corresponds to the surface of the active region, and the position at a depth of about 0.3 μm corresponds to the interface between the element isolation insulating film and silicon substrate. It can be seen that impurities reach a deeper position in the active regions than in the regions just under the active regions.
The p-type well 102 in the active region 106 becomes deeper than the p-type well 102 just under the element isolation insulating film 103, by an amount corresponding to the thickness of the element isolation insulating film 103 and an increase in the depth by the channeling effect. Therefore, the resistance value of the resistor element having the p-type diffusion layers 104 and 105 as its opposite terminals becomes lower than that intended by a designer. Since regions having different thicknesses are mixed, a circuit layout design aiming to obtain a desired resistance value becomes complicated.